This invention relates to the use of initialize words in, for example, read-only memories (ROMs). An initialize word is a binary data word stored in a memory circuit which is placed on the output leads or in an output register of the memory circuit when an initialization signal is received by the memory circuit on an initialize input terminal. One example of a memory device which may use an initialize word is a programmable read-only memory (PROM).
A PROM is a user programmable memory device from which previously stored data is read out in a nondestructive manner. The data to be read is identified by a binary address input signal representing the address of a data word in the PROM. When an address signal corresponding to the address of a stored data word is placed on the address input leads of the PROM, the PROM places that stored data word in the output register of the PROM. From the output register the data word is transferred to the output terminals of the device. PROMs often contain program instructions for a microprocessor or a central processing unit of a computer. In certain circumstances, such as power interruptions or excessively high temperature within the computer, it is necessary to interrupt the normal pattern of program instructions which are provided by the PROM in response to address signals received by the PROM. In such circumstances, it is useful to have the capability to provide a preselected data word in an output register of the PROM in response to an initialize signal received by the PROM on an initialize input terminal.
One method of implementing a PROM is shown in the block diagram of FIG. 1. PROM 30 is a prior art 1K byte PROM which contains one thousand and twenty-four binary data words each containing eight (8) bits. Decoder 1 receives address input signals on address input leads A.sub.4 through A.sub.9 Decoder 1 selects one of output leads 10-1 through 10-64 in response to the address input signals on address input leads A.sub.4 through A.sub.9, places a logical 1 on the selected lead, and places a logical 0 on all the remaining deselected decoder output leads. Leads 10-1 through 10-64 are also the input leads for programmable memory array 2.
Programmable memory array 2 provides 16 eight bit data words in response to the high level signal provided on a selected one of leads 10-1 through 10-64. These sixteen data words are transmitted by data bus 3 to 1:16 multiplexer 4. Multiplexer 4 is controlled by signals from decoder 7, which are transmitted on control bus 11.
Decoder 7 receives input signals on address input leads A.sub.0 through A.sub.3. Control bus 11 includes 16 control leads 11-1 through 11-16. Decoder 7 selects one of control leads 11-1 through 11-16 in response to the signal on address input leads A.sub.0 through A.sub.3, provides a logical 1 on the selected control lead, and provides logical 0 on all the remaining deselected leads of data bus 11. Multiplexer 4 selects one of the 16 eight-bit binary words carried by data bus 3 in response to the signal provided on data bus 11 and provides the selected eight-bit word to output register 6 via data bus 19, initialize word register 5, and data bus 20. Output register 6 provides the selected eight-bit word on output leads 0.sub.0 through 0.sub.7 or, alternatively, the initalize word stored in initialize word register 5.
FIG. 2 is a schematic diagram of one embodiment of programmable array 2 of FIG. 1 which contains an array of 64 rows, each row having 128 memory cells. Input lead 10-X, where X is an integer given by 1.ltoreq.X.ltoreq.64, is connected to the bases of transistors 15-X-1 through 15-X-128. Programmable array 2 is programmed to contain the data desired to be stored in the PROM by selectively opening fuses 16-1-1 through 16-64-128 by means well known in the art (not shown). When a logical 1 is placed on the base of transistor 15-X-Y, where Y is an integer given by 1.ltoreq.Y.ltoreq.128 and when fuse 16-X-Y is intact, the signal on output lead 3-Y is a logical 1. Conversely, when a logical 1 is on the base of transistor 15-X-Y and fuse 16-X-Y is open, the output signal on output lead 3-Y is a logical 0. Therefore, by placing a logical 1 on one selected input lead, 10-X, and by placing a logical 0 on the unselected input leads, the output signal on output leads 3-1 through 3-128 is entirely dependent upon the status of fuses 16-X-1 through 16-X-128. Therefore, 16 eight bit data words are stored in each of the 64 rows of programmable array 2 by selectively opening fuses 16-X-1 through 16-X-128 and 1024 eight bit data words are stored in programmable array 2 by selectively opening fuses 16-1-1 through 16-64-128.
Returning to FIG. 1, when a logical 1 initialize input signal is placed on initialize input terminal 9, the output signal from inverter 8 is a logical 0. When the signal on lead 18 is a logical 0, decoder 7 is enabled and decodes address signals A.sub.0 through A.sub.3, as previously described. The output signals from multiplexer 4 are transmitted by leads 19-1 through 19-8 to the input leads of initialize word circuit 5. When the signal on lead 18 is a logical 0, the signals provided by initialize word register 5 on leads 20-1 through 20-8 are identical to the signals provided by multiplexer 4 on leads 19-1 through 19-8, respectively. Conversely, when a logical 0 initialize input signal is placed on initialize input terminal 9, inverter 8 provides a logical 1 output signal. When the output signal from inverter 8 is a logical 1, decoder 7 is disabled, and logical 0 signals are provided on all leads 11-1 through 11-16, thus disabling multiplexer 4. When the input signal on lead 18 is a logical 1, the signals provided on leads 20-1 through 20-8 are pre-programmed signals contained in initialize word register 5. These pre-programmed data signals are programmed into initialize word circuit 5 using techniques well known in the art, for example in the same fashion that data is stored in the memory cells of array 2. Therefore, when the input signal on lead 18 is a logical 1, the eight bit initialize word stored in initialize word circuit 5 is placed in output register 6 via data bus 20 and thus is provided on output data leads O.sub.0 through O.sub.7 by output register 6.
This initialize word function, whereby a predetermined word is selectively placed in output register 6 in response to an initialize input signal is useful, for example, upon system start-up, restart of the system after power interruptions, and user initiated reinitialization of a computer system. However, although there are many circumstances where an initialize word would be useful, the prior art system shown in FIG. 1 provides only one initialize word.